SiPearl Rhea1: Hardware validation of the European superprocessor
- 5 days ago
- 1 min read
The European semiconductor sector has reached a historic milestone with the power-up of Rhea1 , SiPearl's first microprocessor designed for exascale supercomputers. The French company, closely linked to the EuroHPC initiative, announced on May 13, 2026, the launch of hardware validation for this processor, the first stage of testing and qualification.
The Rhea1 stands out for its complexity: 61 billion transistors and 80 Arm Neoverse V1 cores . These cores, optimized for vector computing and parallel processing, are interconnected by a high-bandwidth internal communication network. Integrated High Bandwidth Memory (HBM ) provides the massive throughput required for HPC applications such as climate simulation, quantum computing, and artificial intelligence. The processor also features DDR5 interfaces for standard memory and 104 PCIe Gen5 lanes , paving the way for fast connections with accelerators and storage networks.
The design of Rhea1 is rooted in digital sovereignty : the chip is optimized for a low performance-to-power ratio and integrates hardware security features (encryption, enclaves). Its modular architecture is designed to evolve across successive generations while meeting exascale requirements. Rhea1 will be integrated into the future Jupiter supercomputer in Germany, demonstrating Europe's capacity to produce cutting-edge processors. This project reflects the collaboration between European industry, research centers, and institutions to reduce dependence on foreign manufacturers.